# Generate Verilog code
hdl:
	sbt run

test:
	sbt test


all:
	sbt "runMain Hello"
	sbt "runMain Max3"
	sbt "runMain MyMAC"
	sbt "runMain MyOperators"
	sbt "runMain ParameterizedAdder"
	sbt "runMain Passthrough"
	sbt "runMain Sort4"
	sbt "runMain Top_bufg"
	sbt "runMain SimpleFsm"
	sbt "runMain PopCount"
	sbt "runMain BcdTable"
	sbt "runMain Cfg_Ticker"
	sbt "runMain addtree"
	sbt "runMain BubbleFifo"
	sbt "runMain Uart"
	sbt "runMain myfifo"

	

test_all:
	sbt "testOnly HelloTest"
	sbt "testOnly MAX3Test"
	sbt "testOnly MyMACTest"
	sbt "testOnly MyModuleTest"
	sbt "testOnly ParameterizedAdderTest"
	sbt "testOnly PassthroughTest"
	sbt "testOnly Sort4Test"
	sbt "testOnly SimpleTestExpect"
	sbt "testOnly TickerTest"


